Appeal No. 1997-0583
Application 08/368,680
The disclosed invention relates to a high speed FIR
filter architecture with precise timing acquisition. The
input to the filter is coupled to a master input of a master
sample and hold circuit. A plurality of slave sample and hold
circuits are coupled to the output of the master sample and
hold circuit. The outputs of these circuits may then be used
in the taps of a FIR filter by multiplexing the outputs to a
plurality of multipliers in a round robin manner. A more
precise sampling is achieved because all the sampling is
controlled by a single master sample and hold circuit. The
slave sample and hold circuits, consequently, need not be high
speed circuits and need not have a precise sampling instant.
Claim 1 reads as follows:
1. An FIR filter having an output, comprising:
a plurality of multipliers, each of said multipliers
including an output and a first multiplier input and a second
multiplier input, each said first multiplier input receiving a
coefficient signal representing an FIR coefficient;
a master sample and hold circuit including a master
output and operable to sample a first input signal and hold
the value of said first input signal on said master output for
a first predetermined period of time;
a plurality of slave sample and hold circuits, each of
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