Appeal No. 1997-0918
Application 08/160,301
said first data register from said left shifted intermediate
data word thereby forming a difference.” The focus of the
argument is that Yamaoka fails to teach subtracting a divisor
from the left shifted intermediate data word. Appellant
continually asserts that this reference operates in such a
manner that the left shifted intermediate data word is the
output of the shifter 2 which is fed to register A0 and not to
the adder/subtractor 1 of Figure 3 of Yamaoka. In the brief
and the various reply briefs appellant argues that Yamaoka
clearly shows that it is the unrotated output of selector 6
that is supplied to the X input of the adder/subtractor 1 of
Figure 3 of this reference. Appellant indicates that the
output of the shifter 2 is stored in register A0 and is not
supplied to the input of this adder/subtractor circuit 1 as
required by claims 1 and 5 on appeal.
For his part, the examiner correctly argues, in our view,
that the claimed feature is recited and taught in the
reference as argued by the examiner in the responsive
arguments portion of the answer at the top of page 8 thereof.
This position is maintained in the succeeding answers.
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