Appeal No. 1997-0918
Application 08/160,301
For our purposes, we make general reference to the
teachings shown in Figure 3 of Yamaoka and the corresponding
discussion at column 3, lines 34 through line 68, the
discussion beginning at topic (d) at column 4, line 63 through
the end of column 5 and, most succinctly, the statements made
in a summary manner at column 6, line 38 through 52.
Thus, it is apparent that in the next succeeding
operation, it may occur that the output of register A0
(previously shifted in shifter 2 before being stored therein)
is operated upon after having been selected by the selector 6
in a subtraction operation performed by the adder/subtractor 1
of Yamaoka. The bottom of page 4 at least of appellant's
initial reply brief indicates in the table that the output of
selector 6 is the intermediate data word for purposes of the
claims. This is consistent with the arguments presented at
page 5 of the initial brief. However, in contrast to
subsequent arguments made in subsequent reply briefs,
appellant asserts in a supplemental reply brief of July 19,
1996, that the operation, as just pointed out by the examiner,
is considered by appellant to be a conditional step where the
5
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