Appeal No. 1997-0923
Application No. 08/400,414
executing operations specified by the decoded
instructions in the functional unit, the executing of a
corresponding reduction operation specified by one of the
decoded instructions in any one of the at least one
functional unit comprising the steps of:
retrieving at least one instruction-
specified input value for the reduction
operation;
producing a Boolean result value having a
first instruction-specified state;
performing an instruction-specified
condition function of one or more of the input
values of the operation to produce a Boolean
condition value, wherein the Boolean condition
value is false for at least one combination of
the input values; and conditionally writing the
result value in an instruction-specified
location in the set of registers if the Boolean
condition value is a second instruction-
specified state.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Conners 4,212,076 Jul. 08, 1980
Faudemay et al. (Faudemay) 5,239,663 Aug. 24, 1993
Claims 21 through 25, 27 through 33, 35, 36, 38, 41
through 44, 46 and 47 stand rejected under 35 U.S.C. § 102(b)
as being anticipated by Conners.
Claims 37, 39, and 40 stand rejected under 35 U.S.C. §
103 as being unpatentable over Faudemay in view of Conners.
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