Ex parte NAKAJIMA - Page 3




              Appeal No. 1997-1038                                                                                          
              Application 08/077,926                                                                                        


                     Representative claim 1 is reproduced below:                                                            
                     1.  A semiconductor device comprising                                                                  
                     (a)  a semiconductor circuit which is an object of a test,                                             
                     (b) an input terminal means receiving an input signal to the semiconductor circuit                     
              during an ordinary operation,                                                                                 
                     (c) an output terminal receiving an output signal from the semiconductor circuit                       
              during the ordinary operation,                                                                                
                     (d) a power terminal applying a specified potential to the semiconductor circuit                       
              during the ordinary operation, and                                                                            
                     (e) a mode switching circuit interposed between the input terminal means and the                       
              semiconductor circuit for switching its operation from the test to the ordinary operation;                    
              wherein                                                                                                       
                     the mode switching circuit (e-1) applies the input signal received on the input                        
              terminal to the semiconductor circuit during the ordinary operation and                                       
                     (e-2) applies at least one specified fixed value to the semiconductor circuit during                   
              the test and, wherein the mode switching circuit receives a test signal which is activated                    
              during the test and deactivated during the ordinary operation,                                                
              wherein the input terminal includes first and second input terminals;                                         
                     and wherein the at least one specified fixed value includes first and second fixed                     
              values,                                                                                                       
                     the mode switching circuit includes a first gate for outputting the first fixed value                  
              regardless of a value of a signal applied to the first input terminal during the test and a                   
              second gate for outputting the second fixed value regardless of a value of a signal applied                   
              to the second input terminal during the test and                                                              
                     wherein the test signal takes the first fixed value when activated or otherwise take                   
              the second fixed value when deactivated                                                                       


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