Appeal No. 1997-1038
Application 08/077,926
wherein the first and second fixed values corresponds to logical values “1" and “0",
respectively, and wherein the first gate includes a first input end connected to the first input
terminal, a second input end receiving the test signal, and an output end outputting a
logical product of a logic value applied to the first input end thereof and an inverted logic
value of the test signal to the semiconductor circuit, and the second gate includes a first
input end connected to the second input terminal, a second input end receiving the test
signal, and an output end outputting a logical sum of logic values of the first and second
input ends to the semiconductor circuit.
There are no references relied on by the examiner.
Claims 1, 6 through 19 and 23 stand rejected under the written description portion
of the first paragraph of 35 U.S.C. § 112. Claims 20, 21 and 23 through 26 stand rejected
under the second paragraph of 35 U.S.C. § 112 as being indefinite.
Rather than repeat the positions of the appellant and the examiner, reference is
made to the briefs and the answer for the respective details thereof.
OPINION
We reverse both rejections.
As to the rejection under the first paragraph of 35 U.S.C.
§ 112, our review of the examiner's position, appellant's arguments, as well as the
specification, drawings and claims presently on appeal all lead us to conclude that the
subject matter questioned by the examiner as to claims 1, 6 through 19 and 23 was
adequately described in the specification as filed to indicate that the appellant had
possession of the presently claimed invention as of the filing date of the application.
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