Appeal No. 1997-1183
Application No. 08/066,362
BACKGROUND
The appellants' invention relates to multiple resonant tunneling circuits for signed
digit multi-valued logic operations. Specifically, appellants’ invention is directed to an
adder of signed digit range-3 base-4 words using negative differential resistance devices.
An understanding of the invention can be derived from a reading of exemplary claim 1,
which is reproduced below.
1. An apparatus for calculating the sum of two numbers, comprising:
signed digit range-3 base-4 words to represent said two numbers; and at
least one device which exhibits negative differential resistance to calculate
the sum.
The prior art references of record relied upon by the Examiner in rejecting the
appealed claims are:
Singh 5,265,044 Nov. 23, 1993
Kawahito et al. (Kawahito), "Multiple-Valued Current Mode Arithmetic
Circuits Based on Redundant Positive-Digit Number Representations",
IEEE, pp. 330-339. (1991)
Kameyama et al. (Kameyama), "Modular Design of Multiple-Valued
Arithmetic VLSI System using Signed-Digit Number System", IEEE,
pp. 355-362. (1990)
Higgins,"Electronics with digital and analog integrated circuits", Chapter 9,
Digital to Analog and Analog to Digital Conversion, pp. 288-289. Published
by Prentice Hall, Inc., N.J. (1983).
2
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