1 Application for patent filed August 27, 1993.
therefor Holsztynski alone, does not meet the requirements of
claims 4 and 5 which depend from claim 3. The inclusion of
Morton in the rejection of claims 4 and 5 does not cure this
deficiency. Additionally, Morton does not meet the added
limitations of claims 4 and 5 as explained with respect to
claim 6. Thus, we will not sustain the 35 U.S.C. § 103
rejection of claim 4 and 5.
With respect to independent claim 14 Appellant
argues:
Claim 14 further requires that the means for
generating a signal indicative of the equality of
first and second multibit operands comprises: a
first input for receiving a signal indicative of the
equality of a selected bit from the first operand
and a selected bit from the second operand; a second
input for receiving a signal indicative of the
equality of previously compared bits from the first
and second operands; means coupled to the first and
second inputs for generating a signal indicative of
the equality of corresponding portions of the first
and second operands, the corresponding portions
comprising the selected bit and the previously
compared bits from the first and second operands.
It is respectfully asserted that neither of
the Batcher or Guttag patents shows this feature.
Batcher’s equivalence function 60, which was relied
on by the final Office Action, merely indicates
equivalence between the single-bit values stored in
the P and G registers. See Batcher, col. 9, lines
15-20. However, Batcher’s equivalence circuit,
which includes the gate 138 (having only two inputs
) does not provide the ability to factor in the
equivalence, or lack thereof, of previously compared
bits of multibit operands. To perform a multibit
equivalence function, it is necessary, at each clock
1 10
1Application for patent filed August 27, 1993.
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