1 Application for patent filed August 27, 1993.
Representative independent claim 6 is reproduced as
follows:
6. A parallel processor comprising:
control input means for receiving control signals; and
a plurality of identical processing cells, each
of the processing cells being connected to at least one
neighboring cell and to the control input means for processing
data in accordance with the control signals;
wherein each of the processing cells comprises:
an arithmetic logic unit (ALU) having an output
representing a carry bit from an arithmetic operation; and
addressable memory means coupled to receive and
store the carry bit from the ALU output in response to a
control signal received by the control input means,
wherein:
the addressable memory means comprises a
plurality of storage locations and an address port for
receiving an address signal, the address signal selecting one
of the storage locations for use in a write or read operation
of the addressable memory means; and
the carry bit from the ALU output is routed to
the addressable memory means without passing through any
intervening clockable storage means.
31
Application for patent filed August 27, 1993.
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