1 Application for patent filed August 27, 1993.
This is a decision on appeal from the final
rejection of claims 1 through 33. Claims 11, 13, 22 and 30
have been canceled by an amendment after final rejection,
paper no. 11. Claims 1, 2, 12, 18, 23, 26 and 31 were
subsequently indicated as allowable in the Examiner’s answer
at page 4.
The invention relates to parallel processor
integrated circuit component, and more particularly to a
Single Instruction Multiple Data (SIMD) array processing unit.
An array of processing cells performs logical or arithmetic
operations on its own data at the same time that all other
cells are processing their own data. At every instant the
same instruction is supplied to each of the cells so that the
logical or arithmetic operation being performed at any instant
in time is identical for all cells in the array. Although
SIMD arrays may be based upon the same generic concepts,
design details can have a great impact on processing cost and
circuit performance. Appellant’s invention optimizes the
arrangement of the Arithmetic Logic Unit (ALU), Random Access
Memory (RAM), global signal generator, identity of equality of
multibit operands, and cell bypass.
21
Application for patent filed August 27, 1993.
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