Appeal No. 97-3082
Application No. 08/650,023
but the examiner has not made such a rejection. However, it
appears to us, from a review of the drawing itself, that there
is no feedback connection between the output of the summing
means, node 46, and the CMOS parasitic P-N junction means,
transistors 28-31. Thus, the drawing, which is part of the
disclosure, is consistent with what is claimed and we find
nothing indefinite about the cited claim language.
Accordingly, we will not sustain the rejection of claims 1 and
4 under 35 U.S.C. § 112, second paragraph.
We now turn to the rejection of the claims under 35
U.S.C.
§ 102(b) as anticipated by Cave. Appellant makes one argument
in this regard and that is that Cave fails to disclose the
claimed “feedback connection absent between said output of
said summing means and said CMOS parasitic P-N junction
means.” Indeed, Cave discloses that there is such a feedback
connection (e.g., see Cave’s abstract).
The examiner does not deny that the feedback path exists
in Cave, directly contrary to the instant claim language, but
argues only that “it is not understood what is meant by the
recitation concerning the ‘feedback connection’ or how such a
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