Appeal No. 1997-3132
Application 08/268,370
employs a scan architecture specified by the IEEE Standard
1149.1 and the second digital circuit employs a scan
architecture different from that of the first digital circuit.
Appellant points out that neither Shiono nor Gruetzner teaches
or suggests the concept of testing an interconnect with
incompatible scan architectures. In particular, Appellant
points out on pages 5 and 6 that Shiono teaches testing an
interconnect using two circuits that are the same and
therefore of compatible scan architectures. Appellant further
points out on page 6 that Gruetzner teaches that the scan
architecture used by the two circuits are the same and
therefore compatible. Appellant states that the references
are absent of any teaching of Appellant's novel feature of the
invention of claim 8, which is the method used to check the
interconnect between the first and second digital circuits
where the first digital circuit employs a scan architecture
specified by the IEEE Standard 1149.1 and the second digital
circuit employs a scan architecture that is different from
that of the first.
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