Appeal No. 1997-3134
Application 08/434,163
said TAP including a first register that receives a first instruction command in said serial format
and converts said first instruction command to a parallel format;
a control register unit that receives, in said serial format, an address to one of said control
registers for data access thereto, said control register unit being coupled to said TAP and said internal
bus;
said control register unit including a second register that converts data received in said serial
format to said parallel format;
in a write operation, said control register unit causing data to be transferred from said second
register to said one of said control registers specified by said address responsive to said first instruction
command;
in a read operation, said control register unit causing data to be transferred from said one of
said control registers to said second register responsive to said first instruction command.
The Examiner relies on the following references:
Swoboda et al. (Swoboda) 5,329,471 July 12, 1994
Andrews 5,459,737 Oct. 17, 1995
Claims 1 through 6, 15 through 17 and 19 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Andrews in view of Swoboda.
Rather than reiterate the arguments of Appellants and the Examiner, reference is made to the
brief and answer for the respective details thereof.
OPINION
We will not sustain the rejection of claims 1 through 6, 15 through 17 and 19 under 35 U.S.C.
§ 103.
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