Appeal No. 1997-4314 Page 2
Application No. 08/155,332
The invention is directed to an address generator for a
memory device. In particular, a dedicated multiplier circuit
for calculating the desired starting address of a read or
write memory operation is included in a disk drive’s address
generator. As it receives data block numbers, the multiplier
circuit multiplies the data block number by a block size value
to quickly generate the physical address. The block size
value is programmable.
Representative independent claim 1 is reproduced as
follows:
1. An address generator for a memory device, the
address generator connecting to a computer peripheral bus and
providing an address to a memory array, the address generator
comprising:
an input port connectable to the computer peripheral bus;
a multiplier circuit operatively connected to the input
port and receiving two multiplicands from the port, a first
multiplicand being a block number and a second multiplicand
being a programmable block length value, the multiplier
circuit providing a product of the two multiplicands; and
an output port operatively connected to the multiplier
and receiving the product, the output port being connected to
the memory array.
The examiner relies on the following references:
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