Appeal No. 1997-4314 Page 3
Application No. 08/155,332
Takasaki et al. (Takasaki) 5,088,031 Feb. 11,
1992
Cassidy et al. (Cassidy) 5,343,426 Aug.
30, 1994
(filed Jun. 11,
1992)
Claims 1 through 6 and 8 through 11 stand rejected under
35 U.S.C. § 103. As evidence of obviousness, the examiner
offers Takasaki with regard to claims 1 through 4 and 8
through 11, adding Cassidy with regard to claims 5 and 6.
Reference is made to the brief and answer for the
respective positions of appellants and the examiner.
OPINION
Turning first to the rejection of independent claims 1
and 9, the examiner contends that Takasaki discloses an
address generator for a memory device as a translation circuit
50A in Figure 7 and that the reference teaches a multiplier
circuit that receives two multiplicands and provides the
product, referring to column 9, line 29 of the reference. The
examiner admits that Takasaki does not specifically teach that
the second multiplicand is “programmable” but the examiner
contends that it is “common knowledge” that any input signal
into a computer “could easily be changed/programmed into a
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