Ex parte INAMORI et al. - Page 2




          Appeal No. 1998-3064                                       Page 2           
          Application No. 08/445,867                                                  





                                     BACKGROUND                                       
               The invention at issue in this appeal relates to a liquid              
          crystal display (LCD).  Specifically, the invention is                      
          circuitry for reading data from and writing data to the                     
          addressable display space of the LCD.  The circuitry includes               
          a common drive circuit and a plurality of segment-drive                     
          circuits.  Under control of a central processing unit (CPU),                
          the circuitry reads data from and writes data to addressable                
          positions of the display space in a row-direction or a column-              
          direction or both.  Such circuitry is particularly useful for               
          LCDS having long rows.                                                      
               Claim 7, which is representative for our purposes,                     
          follows:                                                                    
               7.   A display control circuit for a display unit having               
          a plurality of addressable positions arranged in a matrix,                  
          comprising:                                                                 
                    a plurality of segment drive circuits connected                   
               to the display unit in a line writing/reading                          
               direction, each said segment drive circuit being                       
               provided for the writing/reading of data to/from                       
               only a predetermined addressing range of addressable                   
               positions of a total range of addressable positions                    
               of the matrix, said predetermined addressing range                     
               of addressable positions being in the line                             







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