Appeal No. 1996-1235 Paper No. 33
Application No. 08/067,262 Page 4
1. A method for interleaving a read operation and a
write operation on a bus having a bus cycle time in a
computer system including the bus and a first device,
the method comprising the steps of:
a) operating the first device to transmit a portion
of a write data block on the bus during a first
period, the first period including at least one
bus cycle time;
b) operating the first device to pause for a
preselected number of bus cycle times ;
c) operating the first device to transmit a read
command on the bus during the preselected number
of bus cycle times pause; and
d) operating the first device to transmit a further
portion of the write data block on the bus during
a second period, the second time period including
at least one bus cycle time.
During proceedings in the United States Patent and Trademark
Office, claims are given their broadest reasonable construction
in light of the specification. E.g., In re Sneed, 710 F.2d 1544,
1548, 218 USPQ 385, 388 (Fed. Cir. 1983). The broadest
reasonable interpretation of these limitations in claim 1 is that
part of a write data block is transmitted, then the write
operation is paused for a preselected number of bus cycles during
which a read command is transmitted, and then the write operation
is completed.
Claim 53 does not have the read-during-write-pause
limitation. Instead, claim 53 simply requires that the data
block be transmitted in bursts with a preselected number of bus
cycles in between.
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