Appeal No. 1996-1235 Paper No. 33
Application No. 08/067,262 Page 7
APPENDIX
1. A method for interleaving a read operation and a write
operation on a bus having a bus cycle time in a computer
system including the bus and a first device, the method
comprising the steps of:
a) operating the first device to transmit a
portion of a write data block on the bus
during a first period, the first period
including at least one bus cycle time;
b) operating the first device to pause for a
preselected number of bus cycle times;
c) operating the first device to transmit a read
command on the bus during the preselected
number of bus cycle times pause; and
d) operating the first device to transmit a
further portion of the write data block on
the bus during a second period, the second
time period including at least one bus cycle
time.
(Paper No. 6 (19 Oct. 1992 Amdt.) at 2 and 3.)
53. A memory module comprising:
(a) a random access memory device having inputs
and outputs;
(b) a control logic device having inputs and outputs,
the inputs coupled to a bus having a bus cycle
time, the outputs being coupled to the random
access memory device; [and]
(c) the control logic device providing outputs to the
random access memory device causing the random
access memory device to store a block of data
transmitted on the bus in a plurality of data
bursts interspaced by a preselected number of bus
cycle times.
(Paper No. 5 (Subst. Spec.) at 53.)
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