Appeal No. 1996-1235 Paper No. 33
Application No. 08/067,262 Page 5
Anticipation
Anticipation is established only when a single prior art
reference discloses, either expressly or under the principles of
inherency, each and every element of the claimed invention. In
re Spada, 911 F.2d 705, 707, 15 USPQ2d 1655, 1657 (Fed. Cir.
1990). Gagliardo does not teach interleaving a read command
during a pause in a write operation. The examiner relies on
Gagliardo's write-read data operation (20:42-21:18), but in that
example, the read operation does not occur until after the write
operation is completed. The examiner does not point to a
teaching that the read command is transmitted during a pause in
the write operation. Gagliardo does teach buffering memory
commands while a memory segment is busy (8:12-28), but the
examiner has not pointed out a teaching that any of these
buffered commands are transmitted or that this transmission would
happen within a predetermined number of bus cycles.
Neither the examiner nor Appellants have addressed claim 53
with any specificity. Claim 53 requires that a data block be
transmitted for storage in a plurality of bursts with a
preselected number of bus cycles between each burst. The
examiner has not explained how the portion of Gagliardo that she
relies on (20:42-64) teaches the write operation occurring over a
plurality of bus cycles with interruptions lasting preselected
numbers of bus cycles.
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