Ex parte FAIRBANKS - Page 2

               Appeal No. 1996-4089                                                                                                
               Application 08/227,293                                                                                              


                       The subject matter on appeal is directed to a method for checking logic design rules in a                   

               computer-aided logic design system prior to physical implementation of the logic circuit.  (See                     

               specification, page 1; Brief, page 3).  More specifically, the method involves comparing an initial logic           

               design file with a design rule and notifying a user of any rule violations.  (See specification, page 1;            

               Brief, page 3).  As indicated in the Brief (pages 4 to 8), appellant’s recited logic design verification            

               method applies specific design rules in an effort to check a design and warn a user in the event of an              

               unsatisfactory design.  In general, appellant’s invention recited in claims 17, 18, 20, and 26 on appeal            

               provides for four specific design rules: (1) "to check whether more than one clock signal generation                

               means is used in the logic design" (claims 17 and 26); (2) to check "if more than two gates are present             

               between the clock signal input of a component and the clock signal generation means" (claims 18 and                 

               26); (3) to "determine[] permitted and prohibited clear signal distribution schemes" (claims 20 to 25 and           

               26); and (4) to check "if a synchronous device that is synchronized to a first clock signal receives data           

               that is synchronized to a second clock signal" (claim 26).  As further discussed, infra, we find that the           

               applied references fail to teach or suggest at least specific design rules (1) through (3) as these salient         

               limitations are recited in claims 17, 18, and 20 to 26 on appeal.                                                   

                       Representative method claim 17 is reproduced below:                                                         

                       17.  A method executing in a computer-aided logic design system for designing and testing logic             
               circuitry prior to physical implementation, wherein the method verifies compliance of a logic design with           


Page:  Previous  1  2  3  4  5  6  7  8  Next 

Last modified: November 3, 2007