Appeal No. 1996-4089
Application 08/227,293
supra). We agree, and we find that the features of checking whether more than one clock signal
generation means is used in the logic design (claims 17 and 26), and of checking if more than two gates
are present between the clock signal input of a component and the clock signal generation means
(claims 18 and 26), are neither taught nor would have been suggested by the applied prior art. We
agree with appellant (Brief, pages 9 to 10) that Varma, at the pages cited by the examiners (see Varma,
pages 1055, 1056, 1058, and 1059), fails to teach or suggest the specific rules (e.g., rules (1) and (2))
of claims 17, 18, and 26 on appeal. We cannot agree with the examiners (Answer, pages 9 to 11) that
one of ordinary skill in the art looking at Watkins, and specifically Varma, would have been motivated
to check the specific design rules recited in the claims of checking whether more than one clock signal
generation means is used and of checking if more than two gates are present between the clock signal
input of a component and the clock signal generation means based on the very general rationale of
"identify[ing] real problems in a real ASIC designs" (Varma, page 1063). Accordingly, we cannot
sustain the rejection of claims 17, 18, and 26 under 35 U.S.C. § 103.
We are also in agreement with appellant (Brief, pages 11 to 16) that Watkins and Lipton fail to
teach or suggest the specific design rule recited in claims 20 to 26 (rule (3) as discussed supra). We
find that the specific feature of determining permitted and prohibited clear signal distribution schemes
(claims 20 to 25 and 26) is neither taught nor would have been suggested by the applied prior art. We
cannot agree with the examiners (Answer, pages 5 to 6 and 12 to 15) that one or any of the applied
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