Ex parte FAIRBANKS - Page 3




               Appeal No. 1996-4089                                                                                                
               Application 08/227,293                                                                                              


               a preselected set of design rules that specify logical relationships between electrical signals, wherein the        
               logic design includes one or more electrical signals, wherein the logic design includes clock signal                
               generation means for outputting a clock signal, wherein the clock signal generation means is coupled to             
               one or more components having a clock signal input, the method comprising the following steps:                      

                       providing a design rule to check whether more than one clock signal generation means is used                
               in the logic design;                                                                                                

                       providing a logic design file incorporating the initial logic design in computer-readable form;             

                       comparing at least portions of the initial design to the design rule; and                                   

                       providing a user-discernable indication of any violation of the design rule by the initial logic            
               design.                                                                                                             

                       The following references are relied on by the examiners:                                                    

               Binoeder et al. (Binoeder)            4,620,302                              Oct. 28, 1986                          
               Omoda et al. (Omoda)           4,899,273                             Feb.   6, 1990                                 
               Yoshida                               5,105,374                              Apr. 14, 1992                          

               Watkins et al. (Watkins)              5,220,512                              Jun.  15, 1993                         
                                                     (effectively filed Apr. 19, 1990)                                             

               Lipton                                5,220,662                              Jun.  15, 1993                         
                                                                     (filed Mar. 28, 1991)                                         

               Varma, Prab (Varma), "TDRC - A Symbolic Simulation Based Design For Testability Rules Checker,"                     
               1990 International Test Conference, Paper 46.1, pages 1055-64.                                                      

                       Claims 17 and 18 stand rejected under 35 U.S.C.  103.  As evidence of obviousness, the                     

               examiners rely upon Watkins in view of Varma.                                                                       

                       Claims 20 to 25 stand rejected under 35 U.S.C.  103.  As evidence of obviousness, the                      


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