Appeal No. 1997-0553
Application No. 08/409,191
1. A method for synthesizing a gate level description of an integrated circuit
module including a plurality of circuit blocks from a behavioral description of the module,
comprising:
synthesizing a first block in the plurality of blocks by processing the behavioral
description of the first block to produce a gate level description of the first block;
generating a synthesis shell comprising a gate level description of a circuit having
fewer gates than the gate level description of the first block by reducing the number of
gates in the gate level description of the first circuit block, the synthesis shell having the
same input load and fanout as the first block, output delay relative to clock as the first
block, output drive of the first block, setup/hold constraints on input signals relative to clock
as the first block, and delay from input to output for pass through signals as the first block;
and
synthesizing at least one other block in the plurality of blocks by processing the
behavioral description of the at least one other block with reference to the synthesis shell to
produce a gate level description of the at least one other block.
The prior art references of record relied upon by the examiner in rejecting the
appealed claims are:
Donath et al. (Donath) 4,263,651 Apr. 21, 1981
Drumm et al. (Drumm) 5,029,102 Jul. 02, 1991
Dangelo et al. (Dangelo) 5,222,030 Jun. 22, 1993
Claims 1-28 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Drumm in view of Donath and Dangelo.
Rather than reiterate the conflicting viewpoints advanced by the examiner and the
appellants regarding the above-noted rejections, we make reference to the examiner's
answer (Paper No. 12, mailed Jul. 16, 1996) for the examiner's reasoning in support of the
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