Appeal No. 1997-0553
Application No. 08/409,191
ships or concerns which skilled artisans would have encountered being confronted with
problems involving the synthesis of gate level circuits from a behavioral description.
Specifically, timing and loads are discussed in Dangelo. (See Dangelo at column 3.)
Appellants argue that Drumm attempts to improve the global optimization process
by reducing the gate count that goes into the conventional final optimization. Appellants
contrast the method of the present invention which improves the global optimization
process by performing the global optimization on a circuit description in which the gate
level description of at least one of the logic blocks is replaced by a synthesis shell that acts
as a proxy for the gate level description of the logic block during global optimization. The
shell is generated by reducing the high level description of a functional block to a gate level
description and then replacing the gate
level description with a shell that preserves the essential timing and load information while
eliminating one or more gates. (See brief at pages 4-5.) We disagree with appellants.
Appellants characterize the disclosed invention rather than the invention as
recited in claim 1. The language of claim 1 is silent as to the use of a proxy. Further, we
find that the method does not recite limitations that the logical or computational function is
not necessarily being retained in the gate reduction. (See brief at page 5.)
Appellants argue that the invention can reduce the number of gates much smaller
than Drumm can because the logic function does not have to satisfy the same logic
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