Appeal No. 1997-2112
Application No. 08/398,831
The invention is directed to a method and apparatus for
testing conformance of electronic hardware or software with a
finite state machine model. Claim 14 is reproduced below.
14. A method of generating a Verification Test Sequence
(VTS) for use in testing conformance of a Machine Under Test
(MUT) with a Finite State Machine (FSM) Model, wherein:
said FSM Model has a plurality of Model States (ST) and a
plurality of State Transitions (TR),
each of the plurality of State Transitions (TR) is
located between a First Model State and a Second Model State,
each of the plurality of State Transition (TR) has a
corresponding Input/Output (I/O) Sequence,
each I/O Sequence includes an Input Stimulus and an
Output Response corresponding to the Input Stimulus,
each Input Stimulus comprises an Input Stimulus Signal,
and each Output Response comprises an Output Response Signal,
said method comprising the steps of:
(a) identifying at least one member of each of one or
more Sets of Edge-Under-Test (EUT) Unique I/O Sequence (UIO)
Sets, wherein:
each identified member of each Set of Edge-Under-Test
(EUT) Unique I/O Sequence (UIO) Sets is an Edge-Under-Test
(EUT) Unique I/O Sequence (UIO) Set, each member of each Edge-
Under-Test (EUT) Unique I/O Sequence (UIO) Set is an Edge-
Under-Test (EUT) I/O Sequence,
each Edge-Under-Test (EUT) I/O Sequence is a First
Sequentially Ordered Series of I/O Sequences corresponding to
a First Ordered Sequence of State Transitions,
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