Ex parte GRUETZNER et al. - Page 2

          Appeal No. 1997-3129                                                        
          Application No. 08/301,743                                                  

          application.  An amendment after final rejection filed June                 
          13, 1996, was approved for entry by the Examiner.                           
               The claimed invention relates to a test circuit for                    
          testing the interconnect wiring between two chips of a                      
          plurality of integrated circuit chips.  More particularly,                  
          Appellants indicate at pages 3 and 4 of the specification that              
          selector circuitry on one of the plurality of chips selects                 
          two chips for interconnect testing and enables the transfer of              
          test data between the two chips.                                            
               Claim 1 is illustrative of the invention and reads as                  
               1. A multi-chip semiconductor structure capable of                     
          providing interconnect testing capability, comprising:                      
               a plurality of integrated circuit chips including a first              
          chip and a second chip;                                                     
               said first chip having a first transceiver and a first                 
          storage coupled to said first transceiver;                                  
               said second chip having a second transceiver and a second              
          storage coupled to said second transceiver;                                 
               a selector circuit on one of said plurality of chips and               
          coupled to all of said plurality of chips, said selector                    
          circuit having a circuit portion capable of controlling                     
          selection of said first and said second chip for the                        
          interconnect testing, said selector circuit further capable of              
          selectively enabling said first and said second transceiver to              
          enable transfer of test data from said first storage to said                
          second storage.                                                             

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