Appeal No. 1997-3129
Application No. 08/301,743
After reviewing the arguments of record, we are of the
view that Appellants’ conclusions drawn from the disclosure of
Sauerwald are unwarranted. Contrary to Appellants’ assertion
of “teaching away,” it is our view that Sauerwald’s discussion
of advantages and disadvantages of on-chip testing is nothing
more than a recognition that a circuit designer is faced with
competing objectives (e.g., speed, size, economy) when
deciding to place circuits on-chip or off-chip. We are
convinced that the skilled artisan would have found it obvious
to arbitrarily locate the externally located selection
circuitry illustrated in Figure 4 of Sauerwald to an on-chip
location to address particular test circuit performance
objectives.
We also find the Examiner’s observations at page 7 of the
Answer which point to Appellants’ lack of disclosure of any
advantages resulting from placement of interconnect test
selection circuitry at an on-chip location to be persuasive.
A review of Appellants’ specification reveals that, contrary
to the arguments on appeal, Appellants have recognized the
arbitrary nature of the location of the interconnection
selection circuitry. This is evidenced by Appellants’
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