Ex parte AYLWARD - Page 7

          Appeal No. 1997-3182                                                        
          Application 08/254,643                                                      

          G  and G .  The examiner's rejection mistakenly attributes2     1                                                                    
          features of the sum modifier circuit 26 to the difference                   
          modifier circuit 30 in the answer.  Figure 1 contains circuits              
          which delay the difference (A-B) signals on line 24 and the                 
          sum (A+B) signals on line 20 relative to each other, but not                
          with respect to the left and right input signals per se as                  
          required by the language of the detector circuit quoted above               
          in each independent claim 1 and 21 on appeal.  At most, any                 
          phase shift attributed to the difference signal A-B would not               
          be equal or equivalent to, within 35 U.S.C.  102, the                      
          "relative phase" of the input signals, per se as claimed.  As               
          such, the claimed first multiplier circuit of claim 1 and the               
          multiplier circuit of claim 21 on appeal also cannot be met by              
          the teachings and showings associated with Figure 1 of                      
               Because we have reversed the rejection under 35 U.S.C.                
          102 of independent claims 1 and 21 on appeal, we also reverse               
          the rejection of their respective dependent claims 8 and 22.                
          Furthermore, we reverse the respective rejections of claims                 
          15, 16 and 27 under 35 U.S.C.  103 even in light of the                    


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