Appeal No. 1997-3444
Application 08/268,728
The Examiner finds that Tsukada has a transistor and
means for biasing including a means for varying "all connected
and operating similarly as recited by Applicant" (EA3) and
contends that "all the regions of operation recited in the
claims must inherently exist" (EA10).
The Examiner fails to show how the means for biasing,
means for varying a voltage, and the operations in claim 21
are inherent in the structure of Tsukada. The fact that the
transistor in the Tsukada is an avalanche transistor having a
"latch" mode and is used as a memory element is not, by
itself, sufficient to prove inherency of the specific
structure and operations in claim 21. For example, the
Examiner has not shown that Tsukada is inherently "self-
latched at the boundary between the second and third operating
regions," as claimed, or that the second state is in "said
first operating region," as claimed. Moreover, it is clear
that the memory states are stored in Tsukada at the collector
(translation, page 4) and not at the base, as claimed.
Because the Examiner has failed to carry his burden of
proof to show inherency of the limitations of claim 21 in
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