Appeal No. 1997-3792
Application No. 08/321,334
E. The examiner's § 102 and § 103
rejections of claims 1-3, 5, and 7-10
Although we are of the opinion that the term "maximum
clock frequency" in claims 1-3, 5, and 7-10 renders those
claims indefinite, that indefiniteness is not such as to
preclude us from considering the merits of the examiner's
prior art rejections and concluding that they cannot be
sustained.
Kenny's first embodiment (Fig. 1) is responsive to a
status line 101 (CPUCLKHI) which is "hot" or one when the CPU
clock frequency is fast (e.g., at 33 MHZ) and is "cool" or
zero when the CPU clock is slow (e.g., 1 MHZ) (col. 5, lines
46-49). The status line is periodically sampled by flip-flop
105 in response to a sampling clock signal on line 104 to
produce on line 110 a signal (SMPLHOT) indicating whether the
CPU is "hot" or "cool" (col. 5, lines 52-57). The "hot" and
"cool" signals are accumulated and averaged in an up/down
counter 108, which increments or decrements once for every
sampling of CPU speed (col. 5, lines 58-63). If the count
reaches a binary 1000 (i.e., decimal 8), a FORCESLOW signal is
issued to reduce the CPU clock speed (col. 5, line 64 to col.
6, line 2). After the threshold value is reached, the
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