Appeal No. 1997-3792
Application No. 08/321,334
D. New grounds of rejection under 35 U.S.C. § 112
The following new grounds of rejection under 35 U.S.C. §
112 are hereby entered pursuant to our authority under 37 CFR
§ 1.196(b).
1. Lack of written description support (§ 112, ¶ 1)
Comparing claim 1 to appellants' disclosure, the claimed
"microprocessor" reads on CPU 13 of Figure 1; the claimed
"means for generating a clock signal, said means including
means responsive to a control signal for selecting a maximum
clock signal frequency value" reads on at least register 34b,
multiplexer 36, and phase lock loop circuit 38 of Figure 2.
The multiplexer is responsive to the IDLE/BUSY signal (the
claimed "control signal") to select, during BUSY intervals,
the maximum clock signal frequency value stored in register
34b for application to the input of the phase lock loop
circuit, which generates the corresponding maximum frequency
clock signal.
It would appear that the claimed "means for adjusting the
maximum clock signal frequency value in accordance with idle
and busy operating conditions of the microprocessor" is
intended to be read on adjustment of the maximum clock
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