Appeal No. 1997-3792
Application No. 08/321,334
may not obtain a new maximum clock frequency value from one of
three frequency tables (steps 89, 94, and 92). If the TURBO
option has been asserted (step 91 in Fig. 5B), the supply
voltage to the microprocessor is increased to the required
value (step 93), which can be accomplished using the circuitry
of Figure 3 (Spec. at 14, line 8 to p. 16, line 2). Step 95
represents the act of storing a newly calculated maximum clock
frequency in register 34b (Fig. 2), which stores either the
maximum rated clock frequency of the CPU or the new maximum
clock frequency obtained using the algorithm (Spec. at 13,
lines 15-21). Register 34a stores a minimum clock frequency
value representing the lowest clock frequency capable of
maintaining refresh operations (Spec. at 13, lines 8-15).
Multiplexer 36 is responsive (via state device 31a) to an
IDLE/BUSY bit in control and status register 31 to cause the
multiplexer to select the maximum clock frequency value during
BUSY periods and the minimum clock frequency value during IDLE
periods (Spec. at 12, line 21 to p. 13, lines 2-5). The
selected value is applied to a phase lock loop (PLL) circuit
38, which produces a clock signal having the specified minimum
or maximum frequency.
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Last modified: November 3, 2007