Ex parte WANG - Page 2




          Appeal No. 1997-3793                                                        
          Application 08/294,235                                                      

               This is a decision on appeal under 35 U.S.C. § 134 from                
          the final rejection of claims 1-4 and 12-15.  Claims 1, 3, 12,              
          and 14 were amended (part of Paper No. 18) in response to a                 
          new ground of rejection in the Examiner's Answer and the new                
          rejection was withdrawn (Supplemental Examiner's Answer, Paper              
          No. 19).                                                                    
               We reverse.                                                            


                                     BACKGROUND                                       
               The disclosed invention is directed to a neuron circuit                
          and method of producing a neuron output which multiplies                    
          together a plurality of gated input signals x  and aigi                            
          predetermined weight, where at least one g  is greater than                 
                                                    i                                 
          one.                                                                        
               Claim 1, as amended by the amendment filed July 18, 1997,              
          (part of Paper No. 18) is reproduced below.                                 
               1.  A neuron circuit comprising:                                       
                    a multiplier circuit in communication with a                      
               plurality of gated input signals, each of said gated                   
               input signals representing one of a plurality of inputs                
               to said neuron circuit raised to an exponential power of               
               one of a plurality of gating functions g , said multiplier             
                                                       i                              
               circuit for multiplying said gated input signals together              
               to produce a product and for multiplying said product by               

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