Appeal No. 1997-3842
Application No. 08/385,074
with the examiner's conclusion, even assuming that his initial
assumptions are correct. In Figure 8-11a, each writable block
(according to the examiner's definition) has data in common
with one readable block (again according to the examiner's
definition). However, the claim requires that each writable
block share a memory cell with each readable block, not just
one. Thus, contrary to the examiner's assertion, Hirano fails
to meet the claim limitation.
Further, as stated above, each independent claim requires
that each block of memory cells be simultaneously and
independently readable. The examiner explains (Answer, page
13) that x1 to x4 are simultaneously output by arithmetic
units 8-1 to 8-4, respectively, and concludes (Answer, page
14) that the memory cells, therefore, are simultaneously
readable. The examiner's position becomes a bit clearer at
page 15 of the Answer, where the examiner clarifies that
"since Hirano shows an example wherein arithmetic units 8-1 to
8-4 outputs x1 to x4, respectively ..., from memory 8-11a, it
is considered obvious if not inherent that memory 8-11a is
being accessed by all of the arithmetic units 8-1 to 8-4." In
other words, the examiner apparently believes that all four
5
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007