Appeal No. 1997-3842
Application No. 08/385,074
there must be one read decoder and one write decoder for
reading and writing a picture element from and to memory 8-
11a, respectively.
However, the examiner asserts (Answer, page 13) that "multiple
read and write decoders are ... used when the memory 8-11a is
being accessed/written in a parallel fashion by arithmetic
units 8-1, 8-2, 8-3, and 8-4 so as to provide the picture
elements x1, x2, x3, and x4, respectively for example, within
memory 8-11a." Such a conclusion, however, is based on the
presumption that all four arithmetic units use the same
memory, which we have determined above to be inaccurate.
Thus, the examiner has no basis for his assertion that plural
decoders are used for memory 8-11a. Further, appellant points
out (Brief, page 10) that Hirano does not include plural
decoders, because plural decoders are unnecessary in Hirano's
system, since only a single element is read or written at a
time in each of the memories. Accordingly, Hirano fails to
meet the limitation of plural read and write decoders found in
each of the independent claims.
Since Hirano fails to meet several of the limitations
recited in each independent claim, the examiner has failed to
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