Appeal No. 1997-3842
Application No. 08/385,074
arithmetic units read from the same memory 8-11a, and that
they do so simultaneously to output x1 to x4. Thus, as
advanced by the examiner, since each entry of 8-11a is defined
as a block, and four blocks must be addressed to output the
four picture elements, the blocks are simultaneously readable.
However, as argued by appellants (Brief, page 10), memory
8-11a does not include multiple blocks that can be read
simultaneously. Hirano (column 10, lines 20-21) refers to
"the two-dimensional memories in the arithmetic units 8-2
through 8-4." Thus, each arithmetic unit includes its own
memory 8-11a, and each outputs a different element.
Consequently, that x1 through x4 are output simultaneously is
irrelevant to the question of simultaneous addressability of
the blocks of a single memory. We find no evidence that the
blocks (as defined by the examiner) in any one of the memories
are simultaneously addressable, and, in fact, the output of a
single picture element by each arithmetic unit suggests that
they the blocks are individually addressable, not
simultaneously addressable, as required by the claims.
As to the read and write decoders, both the examiner
(Answer, page 7) and appellants (Brief, page 10) agree that
6
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007