Appeal No. 1997-4125 Page 4
Application No. 08/261,523
Claim 1, which is representative for our purposes,
follows:
1. A data processing system comprising in combination:
a host processor;
a peripheral controller;
an input-output sub-element physically located remotely
from said host processor;
a self-timed interface link coupling host commands and
data directly between said host processor to said input-output
sub-element and said peripheral controller;
said self-timed interface link including a transmitting
node for transmitting a digital data and a clock signal and a
receiving node for receiving said digital data and said clock
signal, said transmitting node connected to said receiving
node by a parallel data bus to individual lines of which
respective bits of digital data streams are coupled in
parallel by said clock signal at said transmitting node; and
said bus including a separate line for transmitting said
clock signal to said receiving node, and said receiving node
including means to phase align said respective bits on each of
said lines separately with respect to said clock signal
transmitted to said receiving node.
The references relied on in rejecting the claims follow:
Read et al. (Read) 4,885,739 Dec. 5, 1989
Murakami et al. (Murakami) 5,113,395 May 12, 1992
Cisneros et al. (Cisneros) 5,166,926 Nov. 24, 1992
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