Appeal No. 1997-4125 Page 8
Application No. 08/261,523
signal which was used to clock the data onto the
individual lines of the bus at the transmitting
node. (First Reply Br. at 8.)
The examiner replies, “it would have been obvious ... to
provide for a clock signal with the means to phase align input
data to allow the use of clock signals with different rates
and to reduce framing errors.” (Examiner’s Answer to Reply
Brief at 6.)
“‘[T]he main purpose of the examination, to which every
application is subjected, is to try to make sure that what
each claim defines is patentable. [T]he name of the game is
the claim ....’” In re Hiniker Co., 150 F.3d 1362, 1369,
47 USPQ2d 1523, 1529 (Fed. Cir. 1998) (quoting Giles S. Rich,
The Extent of the Protection and Interpretation of Claims
--American Perspectives, 21 Int'l Rev. Indus. Prop. &
Copyright L. 497, 499, 501 (1990)). Here, claims 1-3 each
specify in pertinent part the following limitations:
said self-timed interface link including a
transmitting node for transmitting a digital data
and a clock signal and a receiving node for
receiving said digital data and said clock signal,
said transmitting node connected to said receiving
node by a parallel data bus to individual lines of
which respective bits of digital data streams are
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Next
Last modified: November 3, 2007