Appeal No. 1998-0072
Application No. 08/476,786
examiner cites Ishikawa and Bowers as each teaching a dual
port memory having dual address decoders responsive to
address, data and control signals from distinct sources. It
is the examiner’s position that each of Ishikawa and Bowers
teaches address decoders which are programmable to position a
decoder in an address space of the corresponding computer.
The examiner concludes that it would have been obvious to the
artisan to use the dual decoder addressing schemes of Ishikawa
or Bowers with the register file device of Mason [answer,
pages 4-5].
Appellants argue that neither of the cited references
teaches the claimed feature that “‘at least one of said first
and second address decoders is programmable to position it in
an address space’ of the corresponding computer” [brief, page
4]. With respect to Bowers and Ishikawa, appellants argue
that neither reference teaches a programmable decoder and
certainly not a decoder programmable to achieve the function
recited in the claims [brief, pages 5-6; reply brief, page 2].
We agree with the position argued by appellants.
With respect to Ishikawa, we agree with appellants
that the decoders 220 and 320 are not programmable. There is
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