Appeal No. 1998-0072
Application No. 08/476,786
nothing in the translation of the Ishikawa document that would
suggest that either of these decoders is programmable.
Although the examiner states that “[a]ddress decoders 220 and
320 are designed to accept address inputs that place the
memory in an address space of the accessing device (CPU)”
[answer, page 4], there is nothing in Ishikawa to support this
assertion of the examiner. Therefore, the rejection of the
claims based on Mason and Ishikawa is not sustained.
With respect to Bowers, the examiner points to a logic
gate array for teaching the programmability feature of the
decoder as recited in the claims. The examiner states that
“the gate array discussed throughout Bowers is specifically
designed for creating customized logic functions within the
decoders shown in figure 6" [answer, page 5]. According to
the examiner, decoders formed from gate array logic cells meet
the claim limitation quoted above.
We agree with appellants that the decoders in Bowers
are neither programmable nor programmable “to position it in
an address space of said corresponding first or second
computer.” With respect to the quoted function, the examiner
never addresses this limitation specifically. The examiner
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