Appeal No. 1998-0368
Application No. 08/632,183
responding processor bus which, in response to a data transfer
request from the requesting processor, acknowledges the
request so that the requesting processor may continue to run
without stalling. The interface circuit then arbitrates for
the bus of the responding processor and completes the data
transfer between the interface circuit and the responding
processor. The interface circuit then advises the requesting
processor that it is ready for another request, and upon
receipt of another request the interface circuit completes the
prior request with the requesting processor. The interface
circuit comprises storing means for the data to be written or
read and for the address of the location. The interface
circuit also has a control means for managing the requests
from the processors. The invention is further illustrated by
the following claim.
1. An interface circuit for inter-processor data
transfer management comprising:
means coupled between a requesting processor bus and a
responding processor bus for storing in response to a transfer
request initiated by the requesting processor an address and
data, the address being an access address to the responding
processor and the data being data from the requesting
processor for storage at the access address for a write
request or data from the responding processor for transfer
from the access address for a read request; and
2
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