Appeal No. 1998-0368
Application No. 08/632,183
means coupled between the requesting processor bus and
the responding processor bus for controlling the storing means
and for communicating with requesting and responding
processors so that the processors are decoupled from the data
transfer in that the transfer request by the requesting
processor for access to the responding processor is
acknowledged by the controlling means so that the requesting
processor may continue its processing until an interrupt is
received from the controlling means indicating that the
controlling means has completed the request and is ready to
receive another request, and the controlling means arbitrates
for access to the responding processor bus to complete the
data transfer between the responding processor and the storing
means so that the responding processor may continue its
processing while the data transfer takes place;
whereby the interface circuit controls the data transfer
between the requesting and responding processors so that the
processors do not stall during such data transfer.
The references relied on by the Examiner are:
Mercer et al. (Mercer) 4,926,375 May 15, 1990
Mizukami 5,309,567 May 3,
1994
(Filing date: Jan. 24, 1992)
Foster et al. (Foster ‘570) 5,327,570 Jul. 5, 1994
(Filing date: Jul. 22, 1991)
Foster et al. (Foster ‘654) 5,410,654 Apr. 25, 1995
(Filing date: Jul. 22, 1991)
Claims 1 stands rejected under 35 U.S.C. § 103 over
Foster ‘570, Foster ‘654 and Mizukami, while for claims 2 and
3, the Examiner adds Mercer to the combination.
3
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