Appeal No. 1998-0429
Application No. 08/537,187
processors. An understanding of the invention can be derived from a reading of exemplary
claim 6, which is reproduced below.
6. A method for efficiently moving command and data blocks between storage and
one or more auxiliary processors in an information handling system, comprising the steps
of:
building a queue of command blocks for execution by an auxiliary function
processor;
first writing one or more command blocks to memory;
second writing a start address for each command block to an address FIFO
associated with the auxiliary function processor;
reading a command block queue start address by the auxiliary
processor; and
processing the commands in the queue by the auxiliary function processor.
The prior art references of record relied upon by the examiner in rejecting the
appealed claims are:
Andersen et al. (Andersen) 4,409,656 Oct. 11, 1983
Menendez et al. (Menendez) 5,113,494 May 12, 1992
INTEL 8089 Input/Output Processor, iAPX 86/88,186/188 User’s Manual Hardware
Reference, Chapter 4, pp 4-1 to 4-6, 4-15, 4-20 to 4-22 and 4-24 (1985) (INTEL)
Claims 1-10 stand rejected under 35 U.S.C. § 103 as being unpatentable over
INTEL in view of Andersen or Menendez.
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