Appeal No. 1998-0429
Application No. 08/537,187
Appellants argue that the use of the cache memory of the processor increases the
efficiency of the Applicants’ invention. (See brief at page 5.) We agree, but do not
find this limitation to the cache memory in method claim 6. While we agree that INTEL
uses the memory of the processor, it was well known at the time of the invention that cache
memory was faster and more efficient. Therefore, we do not find this argument
persuasive. In our view, the claim language in the independent claims does not include
any details of the manner in which the cache memory operates in the process.
Appellants argue that there is no device polling and no bus traffic. (See brief at
page 6.) Again, appellants do not identify the language in claim 6 to support the argument.
Therefore, we do not find this argument persuasive.
Appellants argue that the use of the FIFO to store the starting address of several
command blocks each of which is automatically executed in turn is not taught by Andersen
or Menendez. (See brief at page 6.) We are not persuaded by this argument either since
we do not find support for it in the language of claim 6. The use of the alternative language
allows interpretation of only one command block which is taught by the prior art as
discussed above.
Appellants argue the coherent read, non-coherent read and snooping, but once
again we do not find any support for these arguments in the language of claim 6. (See
6
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