Appeal No. 1998-0476 Application 08/397,157 no. 16. Claim 7 is the sole claim remaining on appeal. The invention relates to a microcomputer which operates selectively with a non-volatile memory (ROM) and a volatile memory (RAM). A monitoring circuit must be periodically reset, when using the ROM or the RAM, otherwise the microcomputer will be automatically reset. Haphazard changes of the RAM content (for example due to interfering E.M.C. radiation, noise) may allow the monitoring circuit to be reset even though the program flow is irregular. The invention provides for suppression of signals to the monitoring circuit so that it may not be reset automatically when operating the RAM mode. Sole claim 7 is reproduced as follows: 7. A microcomputer, comprising a central processing unit; a non-volatile memory and a volatile memory usable as a [sic] program memories, so that programs executable by said central processing unit are readable into said memories; input/output unit; a monitoring circuit effecting a resetting of the microcomputer when it does not receive any monitoring signal for a predetermined time, the microcomputer operating in at least two different operating states so as to execute a program in said volatile memory in a second operating state; and means for suppressing monitoring signals which are active if the microcomputer is operating in said second operating state; and means for switching the microcomputer from time to -2-Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 NextLast modified: November 3, 2007