Appeal No. 1998-1750
Application No. 08/579,490
an input terminal to which is connected a two-level input signal where
the input signal has a first voltage level which is a high voltage level greater
than a VCC voltage level, and where the input signal has a second level
which is a VCC voltage level;
a PMOS transistor having a source terminal and a substrate terminal,
both connected to the input terminal, said PMOS transistor having a gate
terminal connected to the VCC voltage level, and said PMOS transistor
having a drain terminal;
a shunt NMOS transistor having a drain terminal connected to the
drain terminal of the PMOS transistor, said NMOS transistor having a source
terminal connected to a ground terminal, and said NMOS transistor having a
gate terminal connected to the VCC voltage level, wherein the NMOS
transistor is turned on to provide a shunt resistance between the drain
terminal of the PMOS transistor and ground;
a series-pass NMOS transistor having a drain terminal connected to
the drain terminal of the PMOS transistor, having a source terminal, and
having a gate terminal always connected to a VCC voltage level, wherein the
gate-to-bulk voltage across the PMOS transistor does not exceed 13 v -
VCC.
The examiner relies on the following references:
Ashmore, Jr. 4,862,019 Aug. 29, 1989
Douglas et al. (Douglas) 5,118,968 Jun. 02, 1992
Mahabadi 5,510,735 Apr. 23, 1996
(Filed Dec. 29, 1994
Claims 1 through 4 stand rejected under 35 U.S.C. § 103. As evidence of
obviousness, the examiner cites Douglas with regard to claims 1 through 3, adding
Mahabadi with regard to claim 4.
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