Appeal No. 1998-2116
Application 08/665,760
specifically a method for reducing the power consumption of
the receiver circuit. In response to a rising edge of a bus
clock signal (Brief, page 10, line 4), a first pulse is
generated using logic circuitry (Brief, page 10, lines 5-18).
The beginning of that pulse turns on a differential amplifier
(page 10, lines 5-7), which is used to compare an I/O line
voltage with a reference voltage. The differential amplifier
turns off (Brief, page 10, lines 11-14) in response to the end
of the first pulse.
Claim 48 is reproduced as follows:
48. A method for reducing the power consumption of
a pulsed latch receiver circuit, the method comprising the
steps of:
generating a first pulse using logic circuitry in
response to a rising edge of a bus clock signal;
turning on a differential amplifier in response to
the beginning of the first pulse;
comparing an I/O line voltage to a reference voltage
to generate an output signal from the differential amplifier;
and
turning off the differential amplifier in response
to an end of the first pulse.
The Examiner relies on the following references:
Grundmann et al. (Grundmann) 5,107,462 Apr.
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