Appeal No. 1998-2144
Application No. 08/568,847
transfer through electrical connections (1, 2); and contact means on the backside of the
package (note column 4, lines 46-63).” (Id. at 3.)
The IBM TDB discloses a ceramic cap 1, but no electrical contacts are shown.
(Compare with appellants’ Figure 3, having electrical contacts (I/O pins) 34.) A chip 2 is
shown, which is connected in some fashion to substrate 4. Sumida discloses (Figure 1)
insulator layers 10 having electrically conductive vias 8a through 8c and thermal vias 4.
Column 4, lines 46 through 63 of Sumida refers to “the backside of the package,” but does
not appear to describe any “contact means,” on the backside of the package or anywhere
else.
The IBM TDB and Sumida appear to have similar teachings. As shown in Figure 2
of the IBM TDB, thermally conducting vias 8 are in place for transferring heat from chip 2,
through thermal paste 7, through ceramic cap 1, and to heat sink 5. (Compare appellants’
Figure 3, with columns 66F between backside 26 of chip 12 and cap 64.) Figure 1 of
Sumida shows a package having the general orientation of appellants’ prior art Figure 2,
having chip mounting portion 3 and external terminals on the superior portion of the
package. The thermal vias, however, are situated to remove heat from the backside of a
chip mounted on chip mounting portion 3. The general teachings of the references are
similar, but with orientations -- what constitutes the “backside” of the chip -- differing by 180
degrees.
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