Appeal No. 1998-2712
Application No. 08/478,429
of the memory array, the instant invention provides a counter and decoder in order to step
through contents of the memory one row at a time. The contents of each row are then
sequentially supplied to a single comparator to be compared to an input value held in a
register. Each time a match is found, the row address of the matching memory row is
stored in a stack.
Representative independent claim 1 is reproduced as follows:
1. A content addressable memory, comprising:
a random access memory, organized as a plurality of rows having a
preselected number of bits, each row selectable by a row address;
a counter for sequentially generating row addresses to be presented
to the random access memory;
a register for storing an input value to be compared to the rows of
said memory, said register having a number of bits equal to the number of
bits in each random access memory row;
a single comparator for comparing, in sequence, each selected row
with the value stored in said register, wherein said comparator compares a
row and the value stored in said register in a single step, and for generating
a signal indicative of whether a match occurs; and
means connected to said comparator for storing the row addresses
generated by the counter for each row which causes a signal indicative of a
match to be generated.
The examiner relies on the following references:
Phelps 4,532,606 Jul. 30, 1985
Szczepanek 4,959,811 Sep. 25, 1990
[filed Nov. 03, 1986]
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