Appeal No. 1998-2712
Application No. 08/478,429
With regard to the rejection of claims 1 and 3-16 under 35 U.S.C. § 103, we refer to
pages 4-6 of the answer for the examiner’s explanation of the rejection.
For his part, appellant contends that there are at least three limitations in the claims
which distinguish over the applied prior art:
1. Neither Sczcepanek nor Phelps discloses or suggests a register for storing an
input value which has the same number of bits as each memory row.
2. Neither Sczcepanek nor Phelps discloses or suggests a single comparator for
sequentially comparing an input value to each memory row.
3. Neither Sczcepanek nor Phelps discloses or suggests a means for storing each
row address in the memory containing data matching the input value.
With regard to the second alleged difference concerning a single comparator, it is
not entirely clear how appellant’s comparator is a single comparator, distinct from the
comparators of the prior art. It is true that Phelps, for example, includes a comparator in
each CAM cell while appellant’s comparator (element 20 in Figure 1) is more of a
distinct element. However, even appellant’s single comparator appears to be a series of
comparators since each bit in a row must be separately, albeit simultaneously, compared.
Accordingly, we are not persuaded by appellant’s single comparator argument as a
distinguishing difference over the applied prior art. Additionally, we note
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